For example when constructiong a D-Latch (so called "Delay"-Latch). Input signal doesn't arrive at the same time at the AND-gates and prevents undesired behavior.

Check out my last entry on gate delay: https://ldjam.com/events/ludum-dare/46/tyson-lee-keep-it-alive-edition/another-example-of-propagation-delay-of-logic-gates

Come tinker and play at: https://ldjam.com/events/ludum-dare/46/tyson-lee-keep-it-alive-edition